65.6339.6361

Abstracts for Advanced Packaging Forum

 

Session Chair

Mr. Nelson WONG

Company

Kulicke & Soffa (S) Pte. Ltd.

Designation

VP – Ball Bonder Business Line

Profile

Nelson is the Vice President of Ball Bonder Business Line at Kulicke & Soffa Singapore.

Nelson joined K&S in 1997 as Application Manager before moving on to lead the Ball Bonder Product Management team. 

Prior to joining K&S, Nelson was the Process and Packaging Engineering Manager at STMicroelectronics for 13 years.

Nelson holds an MBA degree and a degree in Physics from National University of Singapore.

 

 

Co-Session Chair

Dr. LEE Teck Kheng

Company

ITE College

Designation

Director of Technology Development Centre

Profile

 

Dr. Lee Teck Kheng received the B.S. degree in mechanical engineering and the M.S. degree in materials science and engineering from the National University of Singapore in 1995 and 1999, respectively and the Ph.D. degree in Mechanical and Aerospace Engineering from the Nanyang Technology University, Singapore, in 2006. He had been with the semiconductor packaging industry for eighteen years, working from the historical package of DIP to the recent flip-chip packages, WLCsp and system-in-package. He joined the Institute of Microelectronics (IME), Singapore, in 1997, researching in the areas of MEMS, CSP, and flip-chip packaging. In 1999, he joined Micron Semiconductor Asia Pte Ltd as a Senior Technical Member, responsible for substrate supplier management and leading some research programs in the field of advanced packaging and material characterization.

He is currently the director of Technology Development Centre for ITE College Central, leading a team of engineers and researchers to support the industries in Semiconductor, Automation, ICT and electronics sector. He has authored and co-authored more than 50 journal and international conferences papers. Currently, he holds 62 U.S patents, pending another 20 patents from issuing. He has/had served as a committee member for EPTC, SEMI and ICMAT conferences. He is also listed as Who’s Who in the World 2013-2015 as well as listee of IBC Leading Engineers of the World since 2013. Currently, he acts as co-convenor to represent Singapore in reviewing IEC standard for Semiconductor and Semiconductor packaging.

 

 

Speaker 1

Mr. Yohei “Fred” SATO

Company

Tokyo Electron Limited

Designation

Director, ATS Marketing Dept. ATSBU 

Title of Presentation

Challenges to Move into New Semiconductor Era

Abstract

Semiconductor industry has been experiencing high growth since its birth, but the rate of growth is slowing down from year 2000. Apparently Smartphone, the recent growth driver, has also started deceleration of its growth speed.  Is semiconductor industry entering into matured market?

If looking back the human history, we would find information revolution has just begun, accelerating the pace of information traffic, and the semiconductor technology as an engine has been and would be a foundation of the revolution, and its importance has never change. Remembering the golden rule of this industry as “ innovation creates its own market” the industry needs to move next growth cycle, providing the technology required for coming information explosion era.

This presentation discusses the technology direction and development strategy to move into new semiconductor era in terms of advanced packaging technology.

Profile

Mr. Sato is managing ATS Marketing Dept. where he is responsible for TEL’s Assembly and Test System products. He joined TEL in 1996 and spend many years for product developments for wafer test area which includes contactor and tester, and now is developing next generation equipment for advanced packaging process and test solution.  

 

 

Speaker 2

Mr. Damo SRINIVAS

Company

Lam Research Corporation

Designation

MD, Business Development

Title of Presentation

Electroplating Challenges and Solutions for High Density Fan Out (HDFO) Packaging

Abstract

The advent of high density fan out (HDFO) enables advanced capabilities in the mobile and networking arena due to smaller form factor and higher I/O counts at a lower cost. It also poses challenges due to the introduction of new process flows. The processes specific to electroplating are megapillars, fine pitch redistribution layers (RDL) and 2-in-1 via/RDL. Megapillars require high plating rate with good coplanarity to be cost effective. The within feature shape is critical along with the purity of the film for prevention of Kirkendall voids. The fine pitch RDL used in HDFO packages need to be defect-free and control of the undercut is very critical. The 2-in-1 via/RDL application requires a single chemistry that can drive bottom up fill in the via concurrent with conformal RDL layer.  In addition, the wafer warpage is high requiring special handling on the electroplating tools.  In this presentation, we plan to present how Lam Research Corporation has developed solutions to all these electroplating challenges on the SABRE® 3D ECD system.

Profile

 

Damo Srinivas rejoined Novellus Systems Inc. in April 2010 and is currently Managing Director of Business Development for the Lam Research equipment portfolio serving the advanced wafer level packaging applications & FEOL Electroplating. Damo has held several key management positions including Vice President, General Manager for the Photoresist and CMP business groups at Novellus and Vice President, Interconnect Technologies at ATMI Inc. 
Damo has also extensive international customer experience working in account management roles for Novellus serving Intel in Hillsboro, OR for 6 years , IBM and alliance partners for 2 years based in Fishkill, NY and 2 years in Hsinchu, Taiwan R.O.C., serving TSMC, UMC, and the rest of the Semiconductor companies based in Taiwan, China and Singapore. 
Damo also has extensive product management and business development experience and has led several new product development for high end value added Semiconductor applications. Damo received his M.S. Degree in Materials Science from Arizona State University, Tempe, AZ USA and B.S. Degree in Metallurgical Engineering from Indian Institute of Technology, Chennai, India.

 

 

Speaker 3

Mr. Aronson LIN

Company

ASE Group (ASE Chungli)

Designation

Director, Central Engineering Development & Engineering Integration

Title of Presentation

Cost effective System-in-Package Solution

Abstract

- Current market solution and requirement for SiP
- What can an OSAT support in assembly technology
- Right technology vs Application
- Key technology for cost/Size reduction

Profile

Aronson Lin is currently the Director of Central Engineering Development, as well as Customer and Engineering Integration at ASE Chungli of ASE Group. He has over 10 years of experience in advanced packaging technology development including MCP, SiP, WLCSP, Bumping and Flip Chip. Aronson receives his master degree from Mechanical Engineering, National Taiwan University.

 

 

Speaker 4

Mr. Farhang YAZDANI

Company

BroadPak Corporation

Designation

President and CEO

Title of Presentation

Packaging Security for the IoT Era

Abstract

As the world embraces the welcoming of IOT era, unprecedented level of security measures are underway to safe guard the connected world. Semiconductor packaging industry is expected to play a dominant role in the secured IOT era. Semiconductor package has long been considered a passive mechanical platform primarily used to integrate and fan-out devices. However, this notion is in transition as the industry pushes toward 2.5D and 3D stacking and semi-intelligent packages. With the heavily outsourced model of 2.5D/3D integration, amplified threats of security breaches are imminent. This talk describes the emerging security challenges and requirements that the packaging industry is facing in the IOT era.

Profile

Farhang Yazdani is the President and CEO of BroadPak Corporation, providing total solution and technologies to develop and launch secured 2.5D/3D products. Through his 17 years with the industry, he has served in various technical, management, and advisory positions with leading semiconductor companies worldwide. He has numerous publications and IPs in the area of 2.5D/3D Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He received his undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle. He is a member of AICHE, ASME, IEEE, IMAPS, SPE and the Society of Rheology.

 

 

Speaker 5

Dr. Tom NI

Company

Advanced Micro-Fabrication Equipment Inc

Designation

Vice President & CTO

Title of Presentation

Deep Si Etching for Advanced Packaging and Various Applications

Abstract

In recent years, the emerging IoT trend and wearable market is driving the demand for the devices using advanced packaging and advanced MEMS sensors. These devices have better performance including higher sensitivity and more novel functionalities. Also, the market demand for scale-down device has driving the demand for more compact package with higher complexity. Deep Si etching is one of the key technologies required for advanced packaging including TSV, 3DIC WLP etc.

However, in comparison with the large IC equipment market, the industrial effort which is put on the advanced packaging equipment t is much less. This has resulted in processing technology of packaging technology capability lagging years behind the IC processing technology, and therefore cannot meet the stringent and demanding requirement for advanced packaging industry.

In this paper, AMEC Primo Deep Silicon Etch will be introduced for IC Packaging Technology. This processing tool is equipped with various technology features that were developed for advanced IC manufacturing processes. It includes Dynamic Frequency Tuning RF source, Symmetrical Chamber Pumping, Advanced Fast Gas Switch Capability, Multi-zone Temperature Control ESC etc.

With all these advanced features, AMEC Primo Deep Si Etch has demonstrated superior performance than the conventional deep Si etching chamber. The unique dual station design also offers the best COO advantage for the advanced packaging customers in addition to the advanced technology.

Profile

Dr. Tom Ni serves as VP, CTO & Etch Product Business Group GM in AMEC.

He manages and leads the Research and Development of Primo D-RIE system, Primo AD-RIE, Primo TSV & ICP Etch which is currently used in the high end dielectric Etch, Silicon Etch applications in Top Tier Logic & Memory Foundries as well as Packaging Fab.  

His main focus is primarily process chamber technology, plasma source, physics and chemistry engineering.

Prior to joining AMEC, he was a principal technologist in New Product Division of Lam Research Corp. Fremont, US where he was the co-inventor of Lam 2300 series etch products.

Dr. Tom Ni received his bachelor degree from University of Science and Technology of China, and received his Ph.D. in Chemistry from University of Texas at Dallas.

He currently has over 40 patents in the field of semiconductor processing apparatus, while authored or co-authored numerous publications.

 

 

Speaker 6

Dr. Shan GAO

Company

GLOBALFOUNDRIES  

Designation

Principal Member of Technical Staff (PMTS), Packaging Technology & Integration (PTI)

Title of Presentation

High Density Fan-Out (HDFO) Technology – Challenges and Opportunities

Abstract

This paper describes GLOBALFOUNDRIES’s HDFO approach. High Density Fan-Out (HDFO) has emerged as one of key enablement for high density and low cost solution, with CMOS scaling becoming more and more difficult for leading edge technologies, advanced interconnect and packaging solutions becomes critical to achieve high density I/O interconnect. Compared with conventional Fan-out wafer lavel package, such as eWLB, HDFO provides significant routing density advantage in the high-speed and high-bandwidth system, which enables AP/memory bandwidth of 26-52GB/Sec for mobility application. In addition, the architecture of HDFO provides package area and thickness reduction benefits over conventional flip chip CSP (FcCSP), in which the reduced thickness is becoming a key product feature for leading brand premium smart phones. This provides tremendous opportunities for HDFO to be used in mobile application. The key challenges in the development of HDFO and proposed solution are presented and discussed. The collaborative supply chain, which GLOBALFOUNDRIES has established for HDFO, ensures the requirement from customer with low cost, technical competitiveness and fast time to market. 

Profile

Shan Gao received Ph.D in Material Science from Technical University of Munich. He is currently the Principal Member of Technical Staff (PMTS) in Packaging Technology & Integration, GLOBALFOUNDRIES, responsible for technology development of Chip Packaging Interaction, 2.5D Silicon Interposer, High Density Fan-Out and OSAT management. He has 18 years’ experience in semiconductor and electronic packaging, including test chip design, wafer & package process development, reliability evaluation and technology qualification. Before joining GLOBALFOUNDRIES, he served various positions in industry and research institute, such as technical manager in Interconnect & Advanced Packaging department, Institute of Microelectronics, senior manager in packaging technology department, Samsung, etc. He has published over 100 international Journal & Conference papers and filed/granted over 20 patents.

 

 

Speaker 7

Dr. Arvind SUNDARRAJAN

Company

Applied Materials Inc

Designation

Head of Asia Product Development Centre

Title of Presentation

Process and Equipment Technology for Advanced Packaging

Abstract

Wafer-level packages have emerged in many different varieties. As mobility and consumer demands continue evolving, varied end-product applications drive different packaging architectures with unique requirements and price points. An ever expanding toolbox for advanced packaging has resulted, each offering technology solutions to improve productivity and overcome equipment and material challenges.

This session will focus on micro-pillars, Cu posts, RDL and polymer treatments and discuss how technical challenges in these areas are being address through Applied Material’s wafer level packaging equipment solutions.

Profile

Dr. Arvind Sundarrajan is the head of Asia Product Development Center for the Singapore office of Applied Materials, Inc.

He brings extensive experience and expertise to his role, where he manages all product development for Applied Material’s Advanced Packaging lab in Asia, a $100M joint lab with A*STAR’s Institute of Microelectronics. He has responsibilities for R&D, concept & feasibility, prototype design and testing, product releases as well as customer management. He is also leading the development of partnerships with research institutes across Asia to develop new concepts and drive disruptive innovation at Applied Materials.

Dr Sundarrajan had notable successes in his R&D career. He has successfully released several physical vapour deposition products, comprising integration, chemical vapour deposition, atomic layer deposition and contact clean technologies. He holds 35 patents and was awarded a Gold Medal by the Indian Institute of Foundrymen, Bombay, India.

Dr Sundarrajan is a member of Governing Board of the Singapore Synchrotron Light Source (SSLS) and NUS Nanoscience and Nanotechnology Initiative (NUSNNI). 

Dr. Sundarrajan joined Applied in 1996 and has held management roles.

 

 

Speaker 8

Mr. Alex NIES

Company

Kulicke & Soffa

Designation

Head of Product Management for Advanced Packaging Mass Reflow Business Line

Title of Presentation

Known Good Package, The New Standard for Mass Reflow S.I.P.

Abstract

In today’s Semiconductor market we see a continuous growth fueled by the Internet of Things (IOT), for Advanced Packaging. Advanced Packaging innovations are needed because lithography innovations only are no longer delivering the cost improvements like in the past. Next to this drive for cost improvements, form factor, thermal performance and electrical performance are playing an important role for further miniaturization and integration.

One of the packages that can reach the highest integration is a System In Package (SIP). SIP is a single package combining one or more IC’s of different technologies with possible other electrical or mechanical parts. IC technologies either wire bonded, FC’s or both can be combined with passive components (SMD’s) as small as 01005 or even 0201metric.

Manufacturing of SIP’s can give some cost challenges. Looking to the cost structure of a typical SIP you can see that these packages start with one or more Know Good Dies (KGD’s). The KGD is by far the most expensive part of a SIP. But next to this KGD, very often multiple passives are placed (sometimes more than 50 passives) into one SIP. Only those KGD’s in combination with multiple passives that are manufactured without defects can become a Known Good Package (KGP). The key here is to manufacture KGP’s without manufacturing defects.

In this presentation the impact of zero defect production on the total manufacturing cost will be addressed. Case studies of cost of non-quality and a full overview of bonding / placement equipment requirements for high quality KGP/ SIP manufacturing will be presented.

Profile

Alex Nies is the Head of Product Management for Advanced Packaging Mass Reflow Business Line at Kulicke & Soffa. He leads the product team to deliver quality equipment and services solutions to the back-end semiconductor and advance packaging market.

Alex has over 27 years of experiences in advanced packaging technologies industries. He started his career as a Product Specialist, after which he became the Asia-Pacific Regional Service Manager based in Singapore. After returning to the Netherlands, he was the Global Key Account Manager and Product Marketing Manager for the development of the successful A-Series equipment platforms. Alex holds a Bachelor Degree in Electronics from Fontys University of Applied Sciences, the Netherlands.

 

 

Speaker 9

Ms. Jan VARDAMAN

Company

TechSearch International Inc.

Designation

Founder and President

Title of Presentation

SiP’s Role in the Expansion of IoT

Abstract

Growing demand for connected devices and systems (commonly referred to as The Internet of Things (IoT) or the Internet of Everything) and the increased deployment of smart devices to collect data, transmit and/or process information is driving new requirements for semiconductor packaging.  This translates into an increasing number of MEMS and sensors, processors, and connectivity devices.  This presentation examines trends in packages such as system-in-package (SiP).  Formats include a variety of SiPs such as leadframe, laminate substrates, fan-out wafer level packages, and other alternatives and discussed.  Challenges in developing these packaging solutions are presented.

Profile

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. 

She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. 

She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China. 

She received the “Die Products Industry Achievement Award,” at the 14th Annual International KGD Packaging and Test Workshop in September 2007 and in 2012 received the IMAPS GBC Partnership award. 

She is a member of IEEE CPMT, SMTA, MEPTEC, IMAPS, and SEMI.  She was elected to two terms on the IEEE CPMT Board of Governors and is an IEEE CPMT Distinguished Lecturer.  

Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.  

She received her B.A. in economics and business from Mercer University in 1979 and her M.A. in economics from the University of Texas in Austin in 1981.

 

 

Speaker 10

Dr. Shang YANG

Company

Advantest (Singapore) Pte. Ltd.

Designation

Senior R&D and Application Engineer

Title of Presentation

Application of Terahertz Time-Domain Spectroscopy on Highly Reliable Encapsulation of Semiconductor Devices

Abstract

The packaging of semiconductor devices is getting more and more challenging in recent years with the demands of both increasing integration density and reducing profile, especially for thin and large die-size packages such as TQFP and LQFP. In view of reliability, cost and productivity, more efficient packaging process control is required not only in the post-process metrology control but also in the pre-process screening of encapsulation materials.

The terahertz (THz) time-domain spectroscopy (TDS) technology by Advantest Corporation provides a rapid and non-destructive method for the quality control in the packaging process from both material characterization and structure metrology perspectives. Compared to the other non-destructive imaging techniques such as X-ray, Microwave or SAT (scanning acoustic tomographic), THz-TDS has many advantages in terms of speed, resolution, reliability as well as operation safeness.

Profile

Dr. Yang Shang is currently a senior R&D and application engineer at ADVANTEST Singapore, working on various applications of terahertz technology. After he obtained his honored B.S. degree in electrical and electronic engineering from Nanyang Technological University (NTU) in 2005, he spent more than 5 years’ work on the measurement equipment and system design in the satellite communication industry, within which period he received his M.S. degree in 2009 from NTU. Then he was selected by the Joint Industry Postgraduate (JIP) Programme of Singapore Economic Development Board (EDB), spending 3 years in Virtus IC Design Centre of Excellence in NTU and obtained his Ph. D degree in February 2015, with major of terahertz integrated circuit design and applications.  

Dr. Yang Shang has 31 peer-reviewed and referred publications [conference (19) and journal (12)], 1 book chapter co-published on the IC Package System Integrated Design, 1 book will be published on terahertz integrated circuit design, and 1 patent application in pending. He was also the student paper competition finalists in IEEE SiRF’13 and RFIC’13, and received his best paper award at IEEE Singapore MTT/AP Chapter in 2014 and excellent patent award at ADVANTEST in 2015.

 

 

Speaker 11

Mr. Kenny CHIONG Kung Chuan

Company

Indium Corporation

Designation

Senior Technical Support Engineer

Title of Presentation

Ultralow Residue No Clean Material for Advanced Packaging Assembly

Abstract

Recent years have seen rapid development in the area of advanced packaging which is primarily driven by the rapid growth in mobile handheld device. The replacement of the standard flip-chip solder bumps by fine pitch copper pillar bumps has becoming a new increasing trend. Driving this trend is the demand for increased functionality and performance in smaller or thinner devices, so called “Microfabrication”. As a result, the finer pitches and narrower standoff (height of the die-to-substrate) become challenges for the assemblers. Traditionally, the solder-based packaging interconnect method is through flip-chip attachment to the carrier (either substrate or lead frame) using solder that is assisted by flux acts as a medium for removing oxides.

With the water-soluble flux as a dominant trend in the industry, aqueous cleaning of the flip-chip flux residue becomes more challenging for the package with reduced standoff and finer pitches. This is followed by the emerging failure mode where damage to the thinned chip itself and the subsequent yield loss during aqueous jet impingement and drying processes. Hence, the gradual shift towards using semiconductor-grade ultra-low residue no-clean fluxes, which eliminates the cleaning process, is inevitable. The flux residue left behind after soldering process is very minimal for these fluxes, and compatible with the underfill or molding material used in the subsequent process. This paper discusses the variety of new and emerging challenges in the flip-chip attachment process, including the use of different types of flip-chip flux. Concerns involving the application of the flux, the reflow process, the cleaning process, and compatibility with the underfill will be discussed in detail.

Profile

Kenny Chiong is the Senior Technical Support Engineer from Indium Corporation and is based in Singapore. He provides the technical support for Indium Corporation’s full product range in the Southeast Asia region, which covers Malaysia, Singapore, and Indonesia. Working closely with customers in the semiconductor and surface mount technology industries, he assists them optimize their processes, troubleshoots, and offers solutions for the process challenges. Kenny has 7 years of experience, primarily in the areas of PCB assembly and surface mount technology. He earned his bachelor’s degree in mechanical engineering, majoring in advanced manufacturing system. Kenny is an SMTA-certified Process Engineer and has earned his Six Sigma Green Belt.

 

 

Speaker 12

Mr. Nelson FAN

Company

ASM Technology Singapore Pte Ltd

Designation

VP of Business Development

Title of Presentation

SiP (System-in-package) Application in IoT and its Requirements on Manufacturing Equipment

Abstract

Era of “Internet of Things” (IoT) is coming, for which it has been realized to be the next big wave after a more than decade long “Mobile era”. Internet of Things, sometimes is also known as Internet of “Smart” Things, is actually an extension of mobile connection in which it connects to almost everything such as our cars, houses, buildings and even cities. It is estimated that more than 50B “Things” would be connected by year of 2020. To make it happen, the “Things” themselves will need to be embedded with many electronics, sensors and connectivity, to enable the sensing, tracking, controlling, communicating and data exchanging. This application change is now driving our packaging industry in a new way.

From application point of view, the device is driven to be long sustainable and more compact. The device and package both require lower power consumption, higher level of integration, and to keep in small size and high performance. SiP (System-in-package) would be a good alternative by its nature of highly integration and promising scaling ability. Think about a package that can be embedded with sensor, power controller, RF, antenna and memory in a tiny package space, while that is probably what a SiP module can do.

SiP (System-in-package), by definition, is an integration of more than one active component with different functionality plus optional passives and other device/s to be assembled into single package to provide integrated functions. Successful cases have been demonstrated such as the Apple Watch. Multiple ICs either in form of flip-chip or wire-bond or both, together with other sensor/s and passive components are attached onto a substrate in strip form. To further reduce the package thickness and cost of making, Fan-out Technology in both large area Wafer form and Panel form are being considered and developed recently. There are also passive and active embedded technologies are being integrated. Since a SiP package contains multiple die and many passive components presented in different formats such as in wafer form, Tape & Reel form or bulk form, to have a right Die Attach equipment is an important consideration to cope with various kind of bond modes and different substrate format to result with a cost effective process. It is also essential to have the optimal downstream process such as encapsulation, balling, and test and finishing to ensure the overall yield and cost of ownership are being well managed.

Profile

Nelson Fan has been serving the semiconductor industry for more than 20 years, who is now the VP of Business Development for Advanced Packaging Technology in ASMPT.  Previously he had been a company Co-Founder and VP of Engineering for a company offering thermal cooling solution, and before that he was the GM and VP of package development of an OSAT in Hong Kong.  Fan holds more than 40 U.S. patents in semiconductor packaging technologies

 

 

 

 

Share page with AddThis