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System-Level-Test for NPI to High Volume

Thursday, May 09
10:25am to 10:50am

IC that are designed often applicable to Varity of application , which all of them may not be known to the Chip manufacturers in the beginning. In the event the Chip being dominant digital content such as CPU / MCU the application could be very wide for which all the possible application specific test cases may not be tested during ATE test flow. Also the ATE test flow is more focused on validating individual Structure / Blocks of the IC not much focused on the testing it as per the End application usage. System-level test SLT can be looked upon as the ability to test a chip, or multiple chips in a package, keeping the need of how it ultimately will be used by running customer specific use cases.

This presentation talks about the various development happenings in the area of MEMS , FPGAs and Handlers that are designed for keeping SLT in mind that could bring changes to the way we test the device for NPI to High volume.

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