Tutorial Session on Electrical Fault Isolation


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Event Date Venue

Advanced Semiconductor Technology Conference (ASTC)

 October 6-7, 2016    Singapore 

FLEX Southeast Asia

 October 6-7, 2016    Singapore

Please contact Ms Shannen Koh at skoh@semi.org for more details.


Wednesday, 27 April 2016 | 13:30 – 17:00hrs
Spice Arena (Conference Room 2 & 3, Level 2), Penang, Malaysia

Organised by:



Unleash the Power of combining Test and Electrical Failure Analysis for Failure Diagnostic: Dynamic Electrical Fault Isolation



In this era of sub-28nm nanotechnology, it is well-known that precise control of pattern fidelity is becoming more challenging. This is compounded by the shrinking process window due to reducing design margins. The outcome is an increase occurrence of product logic failure and circuitries not achieving performance specifications. In order to maintain a fast yield ramp, failure debug approaches have to be both effective and efficient to ensure root cause learning in the shortest possible time.

Product logic debug has always been considered a challenge due to the lack of control and observation probe points on modern system-on-chips (SoCs). Semiconductor testing is able to diagnose/ characterize fail modes while electrical failure analysis (EFA), or fault isolation, is necessary to locate the failing location in the device. Experts in each domain possess distinct knowledge and plays markedly different roles in the failure debug value chain. However, both encounter limitations to fully address contemporary issues.

This tutorial demonstrates how a synergy of test and EFA can derive advanced interdisciplinary methods and workflows that are capable to overcome current technical gaps in debug. One focus area is the hardware setup, which includes test sockets, EFA tool modifications and other considerations for dynamic EFA. Another area of focus is the test program/ pattern requirements and communication interface between the tester and EFA tool. The success of such methodologies also relies to a large extent on the involvement of chip designers and this is evident in the application test cases that will be presented.

There is growing interest in this area in the design debug community and the content is aimed at equipping failure analysts, test/ EFA hardware suppliers, test engineers and designers with fundamentals of dynamic EFA for a seamless collaboration. It also serves in raising awareness to yield engineers on the role of dynamic EFA for fast yield learning.


Session Chair:



  Dr. GOH Szu Huat
  Manager, GLOBALFOUNDRIES, Singapore






Welcome Remarks by Session Chair


  • Faster Time-to-Market: Foundry’s Perspective
  • Challenges in Advanced Technology Yield Ramp              




Fundamentals of Electrical Failure Analysis (EFA)

  • Terminologies
  • Laser Stimulation: OBIRCH, TIVA
  • Electroluminescence: Photon Emission
  • Black Body Radiation: IR Thermography
  • Solid Immersion Lens Technology
  • Limitations of Static EFA




Semiconductor Test Fundamentals

  • Semiconductor Test Terminologies
  • Interpreting Typical Test Pattern
  • Relevant ATE Tools for Device Failure Characterization and Debug




Break & Networking Time



Combining EFA and Test for Product Logic Debug: Tester-based or Dynamic EFA

  • Introduction to Common Design for Testability (DFT) on Silicon-on-Chip (SoC)
  • Purpose for Dynamic EFA
  • Types of Interface
  • Hardware Design Considerations
  • Software Control Considerations
  • Enhanced Workflow for Dynamic EFA




Test Cases and Discussion 

  • Test cases: IDDQ, JTAG/ boundary Scan, BIST, PLL, Scan Chain integrity, Soft Defect Localization





  • Evaluation on Industry Gaps in Product Yield Ramp
  • Roadmap




Question and Answer 



Closing Remarks by Session Chair





Program subject to change without prior notice.




















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