Dr. TAN Yik Yee

Yik Yee (YY) Tan Ph.D. is a Principal Technology & Market Analyst, Semiconductor Packaging & Assembly at Yole Group. Dr. Tan holds a Ph.D. in Engineering from Multimedia University (MMU, Malaysia). She has more than 25 years of experience in semiconductor packaging. She is also the IEEE Electronics Packaging Society (EPS) Board of Governors, R10 members-at-large.

Based on her technical expertise and market knowledge, she develops technology & market reports and is engaged in dedicated custom projects. Prior to Yole, Dr. Tan worked as a failure analyst and interconnect champion at Infineon Technologies (Malaysia) and later as an open innovation senior manager at Onsemi (Malaysia). 

She published more than 30 papers and hold 4 patents and award winner for IEEE EPS - Regional 10 Contribution Award 2024 and IEEE Malaysia Section – Outstanding Industry Volunteer Award 2024.  

Presentation Title

The Intensifying Race in Panel-Level Packaging

Driven by rapid growth in AI, automotive, and high-performance applications, advanced packaging has become a key enabler of system-level integration as traditional scaling reaches its limits. Among emerging solutions, panel-level packaging (PLP) is gaining renewed attention for its potential to deliver cost efficiency, higher throughput, and larger form factors compared to wafer-based approaches.

Initially adopted for cost down and high-volume manufacturing such as PMICs, RF IC and QFN package replacement, PLP is now being reconsidered for more advanced applications, including AI-driven systems requiring larger and more complex packages. This evolution is accelerating competition across the ecosystem, with OSATs, IDMs, and equipment suppliers actively investing to address key challenges such as warpage, yield control, and process uniformity.

This presentation provides an overview of PLP’s transition from low- to high-end applications, along with market perspectives and supply chain readiness. It highlights the level of supply chain maturity and identifies the critical technological challenges that must be addressed for broader adoption. Ultimately, highlights how these dynamics are intensifying the race in panel-level packaging and redefining competitive positioning across the semiconductor value chain.

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