Mr. Shrikar Bhagath

Shrikar Bhagath is the Vice President of Package Technology Development and Integration at Western Digital. Shrikar has nearly 30 years of package development experience in the automotive electronics, microprocessor, optical networking and flash memory industries.

Shrikar’s currently leads a cross-functional global organization responsible for NAND and SSD Assembly Process Development and Package Integration. His organization is responsible for ideation, development, qualification and ramp to high volume manufacturing of leadership packaging technologies including ultra-thin 3D NAND die stack packages, flipchip and hybrid chipscale packages as well as various standard and emerging form factors of high-density SSD drives.

During his time at Western Digital and previously SanDisk, his team has been responsible for the package development of several industry leading NAND flash products such as the finger-nail sized microSD card, several generations of the eMMC and UHS products for the mobile, automotive and IoT markets, Client SSD drives for the compute and gaming segments and high capacity Enterprise SSD drives for the datacenter market.

Presentation Title

Flash Packaging – Is a Paradigm Shift on the Horizon?

Presentation Abstract

175 Zettabytes (that is 175 trillion gigabytes or 175 followed by 21 zeros !!) is how much data IDC predicts will be generated worldwide by 2025¹. It is estimated that users upload 500 hours of video to YouTube alone every minute²!  With this kind of data explosion, it is only natural that the demand for data storage is surging. The need for faster and faster data transfer rates and higher bandwidths in an energy efficient manner have led to a surge in demand for NAND flash memory based storage solutions such as SSD drives for client and enterprise applications, USB drives and memory cards for consumer applications and embedded storage solutions for mobile phones, automotive and IoT end uses.

In order to scale the storage capacity of a NAND die in a cost-efficient manner and to overcome some of the physical and electrical scaling limitations, the industry replaced planar 2D NAND with vertical 3D NAND several years ago. In 3D NAND, the memory cells are stacked vertically in multiple layers to achieve higher density, lower power consumption and faster read/write speeds all at a lower cost per gigabyte. 3D NAND has matured significantly over the years and is currently in its 8^th generation at most major manufacturers.  The number of active layers has rapidly increased and now stands at over 200 layers in the most advanced nodes.

This 3D vertical scaling of the NAND as well as the architectural scaling from CMOS near Array (CnA) to CMOS under Array (CuA) to CMOS bonded to Array (CBA) creates some unique chip packaging interaction challenges for the industry.  The ASIC controller die, meanwhile, is also going through its nodal shrinks and the final product be it a NAND flash component, an SSD drive or one of the new storage architectures still in their infancy are all bringing new mechanical, thermal and electrical packaging challenges to the forefront. It appears that we will soon be approaching a point, where evolutionary packaging and assembly improvements might not be sufficient and newer, bolder and more innovative solutions and technologies will be needed from the industry to further the Flash product roadmaps.

This talk will attempt to outline where the Flash packaging state of the art is today, the potentially paradigm shifting challenges it faces in the coming generations and the industry wide collaboration and ecosystem development needed to get there in a timely, reliable and cost-efficient manner.

¹ International Data Corporation (IDC) “Data Age 2025” study

² Domo.com/data-never-sleeps

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