Dr. Rose GUINO

Rose Guino, PhD

Head of Application Engineering, Southeast Asia of Henkel Adhesive Technologies, Electronics.

Rose Guino has been with Henkel since 2007. She is based in Irvine, California and is currently on assignment in Southeast Asia as the Manager Application Engineering. She has more than 18 years of experience in Advanced Packaging & Semiconductor Packaging Materials. She was a pioneer for the industry’s first Thermal Compression Non-Conductive Paste (TC-NCP) that enabled fine pitch Cu pillar flip chip, as well as the Non-Conductive Film (NCF) that enabled the 3D TSV stack for high bandwidth memory.

She has a PhD in Polymer Chemistry from the University of Connecticut and was a post-doctoral Fellow in the Materials Research Lab at the University of California, Santa Barbara.

Presentation Title

Advanced Packaging Material Innovations Addressing Mechanical, Thermal, and Reliability Challenges in High-Performance Computing Applications

Abstract

Artificial Intelligence (AI) enabled by the power of high-performance computing devices is rapidly changing the pace of innovation across various industries. Compelling use cases are being imagined daily for applications in consumer, healthcare, finance, automotive, industrial, and other industries. All these applications depend heavily on accessing the AI computational power in both cloud devices in data centers and edge devices in our hands or in machines that serve the consumers locally. The performance of the underlying processors and memory in these devices are reaching new heights enabled by front-end node scaling using extreme ultra-violet (EUV) lithography and back-end using heterogeneous integration methods of 2.5D, 3D, and high-density fan-out (HDFO) technologies. While heterogeneous integration of chips is the preferred approach to enable high-performance computing systems, many processing and reliability challenges arise when assembling multiple functional chips and memory into a single system. This study will present Henkel’s recent developments in advanced packaging materials to address these challenges.

The cloud semiconductor devices in data centers serve processing, networking, and storage needs. Across all these applications, the devices ideally require unrestricted access to processing power and large memory banks, which are predominantly enabled by the heterogeneous integration architecture of chipset-style large and small dies in very large body packages. These packages consume high power during use and are susceptible to high stress, warpage, and thermo-mechanical challenges affecting reliability and performance. We have developed a platform of high thermal underfills, and lid/stiffener attach adhesives that address heat dissipation, package co-planarity, and stress management and improve the dimensional stability of large body packages.

Advanced processors in server and mobile applications often use 2.5D, 3D, and package-on-package (PoP) architectures to stack chiplets. Here, wafer-level molding and underfill processes are needed. Challenges arise in managing in-process warpage, especially during fan-out or wafer-level over-molding applications. Advanced processors and stacked memory architectures have recently demanded molded underfill materials to address throughput, process complexities, and overall cost in 3D stacking and assembly. We will present our innovations in fine filler liquid compression molding and molded underfill materials to address the near-term and long-term roadmaps for 2.5D and 3D packaging to resolve warpage issues while demonstrating good flow and void-free filling capabilities at a wafer-level across fine-pitch (<30µm) and small gaps (<15µm) using our test vehicles.

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