Dr. David HAYNES
Managing Director, CSBG Strategic Marketing, Lam Research, United Kingdom
David gained a B.Eng and PhD in Materials Engineering from Swansea University. His PhD thesis was in the field of organic semiconductors for electronic and optoelectronic applications.
In his professional career, David has accrued more than 20 years of experience in the Semiconductor Capital Equipment and research instrumentation sectors with STS, SPTS and Oxford Instruments. Focused on new technology development, he has a strong process background in plasma etch and deposition for optoelectronics, photonics, MEMS, Power and RF Electronics, as well as advanced chip packaging technologies.
Building on this technical knowledge, David has a proven track record in developing strategic business partnerships; specialising in new technology developments and introduction of enabling process capabilities to leading semiconductor fabs worldwide.
David Joined Lam Research in June 2016 and is currently Managing Director of Strategic Marketing in Lam’s Customer Support Business Group.
Presentation Title:
Enabling Process Solutions for the Fabrication of GaN Based Devices
GaN is one of a new breed of wide bandgap semiconductors that are establishing themselves in a number of key applications. Of course, GaN on sapphire technology is already well established in optoelectronic applications and GaN on SiC is widely used in high power RF applications. But GaN on Si technology has the potential to combine GaN’s optoelectronic, high power handling and RF properties with the scale and larger wafer formats associated with CMOS processing. Indeed, 200mm GaN on Si, and in the future 300mm GaN on Si will unlock the potential of GaN device processing in the well-established CMOS foundry ecosystem.
Despite the considerable advantages of GaN on Si devices, there are numerous process and fabrication challenges that need to be addressed to ensure the continued evolution and commercial adoption of the technology. The need to continue to optimize MOCVD growth of GaN on Si is well understood, but there is also a requirement to develop enabling ultra-low damage etch and dielectric deposition processes for GaN device fabrication, as well as single wafer clean solutions, to manage Ga contamination and ensure compatibility with CMOS processing.
In this paper we will discuss some of these challenges, focusing particularly on how atomic layer etch (ALE) processes can be combined with conventional steady state etching of GaN, to achieve ultra-low damage, atomic scale precision processing of GaN structures for power device, RF and micro-LED applications.