Mr. Nirbhaya PATHAK
Senior Director, Packaging Technology Development & Integration Western Digital Storage Malaysia
Nirbhaya Pathak is the Senior Director of global SSD Platform Development at WD Penang facility in Western Digital. He is an accomplished techno - business leader with 27 years of research & development and manufacturing experience from various technology domains including semiconductor, cellular, storage and microwaves.
Nirbhaya has previously held senior leadership positions in Motorola, and Hughes Network Systems, starting his career as a Defense Scientist. His current contributions on the adoption of Industry Revolution 4.0 (4IR) technology, in the area of machine and deep learning, has contributed towards Western Digital being named Malaysia’s first Lighthouse by World Economic Forum.
Nirbhaya has published many international papers in IEEE conferences. He is an astute business thinker, and his passion lies in amalgamation of technology and business to deliver maximum value to customers.
Presentation Title:
Flash Packaging - Emerging Trends and Integration Challenges
While the Moore’s law guided litho shrinks have resulted in phenomenal increase of planar density in logic semiconductor devices, advances in memory technologies have enabled significant density improvements in the third dimension, in the device as well as packaging over the years. As per Yole Development (a market research and strategy development company), the memory packaging market will grow to US $19.8 billion by 2026 with a 7% CAGR (2020-2026). The riveting pace of Chinese investment in memory technologies, the current growth of flip chip DRAM coupled with the migration to TSV, and the exponential rise of 3D stacking NAND technologies are creating additional opportunities for memory packaging companies. With these trends, NAND and DRAM revenues are expected to grow with a CAGR (2020-2026) of 9% (NAND) and 15% (DRAM) by 2026 to US $92 billion and US $157 billion, respectively.
As Moore’s law limitations began to surface, advancements in the packaging technologies, along with the emergence of Compute-Storage intensive applications, has brought back-end processing – as opposed to front-end processing - to the center stage to improve the performance, compactness, and functionality of IC products. Evolution of the 3D Stacking of DRAM dies using TSVs and thermo compression bonding, and lateral, vertical, logical and architectural scaling of NAND have led to the new high density, high bandwidth memory solutions for systems. However, adopting new technologies like the W2W and D2W bonding with TSVs in the devices require a significant amount of CAPEX. This will drive efforts to extract higher system level performance with current technologies, forming partnerships to develop and implement newer technologies, and most critically ensuring the highest system level performance at the lowest cost possible.
Western Digital is poised to manage the new technology transitions and meet storage solution needs across various segments (Client, Data Centers, Content Solutions, Mobile and Automotive) through its world class manufacturing capabilities (recognized by the World Economic Forum through its Lighthouse certification), and best-in-class memory scientists and systems engineers. The talk presented in SEMICON will highlight some of these topics including rich mix of SSD solutions optimized for power, performance and cost, as well as discuss how the industry can collaborate to meet the gargantuan storage need of the digital universe.