Mr. Terrence TAN
Senior Principal Engineer Intel Microelectronics, Malaysia
Terrence has been with Intel Malaysia for 16 years. Terrence has been a Test Technologist for his entire career. Terrence is currently a Senior Principal Engineer in Manufacturing and Product Engineering Organization. He is passionate about end-to-end product development, solving complex test/manufacturing issues and delivering the product in cost competitive manner. His expertise is on DFT architecture, HVM test flow, Intel Foveros Technology, Test/Debug for Heterogenous Integration and Creating analog/digital test content. He holds 4 patents related to areas of Foveros Test and Analog IO Test.
Presentation Title:
Paradigm Shift in Testability and Diagnosis as Industry Moves to Heterogenous Product Integration
We are moving into the era of heterogenous product integration to keep extending Moore’s Law. Industry is moving at rapid pace to build chips using various advance packaging technology by combining chiplets from different process node and technology. Heterogenous integration have significant impact on production test, both at wafer level and at final test. Debug and fault isolation is a key aspect when come to test. Heterogenous integration has created multiple challenges in physical debug, fault isolation and dealing with field returns. A known good die (KGD) does not mean all shipped bare die will pass at package and system. The final package integration will need to deliver high quality and high yield packaged products.
This keynote provides an overview of test and debug complexity and its economics brought about by heterogenous integration and what are the existing best-known method to build a manufacturable product with chiplets. We will need a high degree of innovation and collaboration among the industry to address all these challenges.