From ATE to Optical: The Testing Playbook for AI-Era Hardware
Day 0 | Monday, 4 May 2026 | 08:30 - 17:30
Room @my5-6, Level 1A, MITEC
Early Bird Rate (Till 15 April)
| Published Rate (16 April onwards)
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AI hardware is no longer limited by compute alone — it’s increasingly limited by data movement. That’s why silicon photonics (SiPh) is emerging as a key technology for next-generation AI chip interconnects. This session brings together two worlds that now must work as one: ATE-based IC testing and photonic testing, with a strong focus on the More-than-Moore era.
On the IC side, we cover how real test flows are built and used in industry: test program structure, digital/parametric measurements, continuity/leakage checks, limit setting, and practical fault isolation and debug—how engineers triage failures and turn test results into yield-learning actions. We also highlight how test strategies evolve across More-than-Moore technologies such as CIS, advanced memory (MRAM and Flash), and mixed-technology devices.
We then connect this foundation to silicon photonics testing: the importance of alignment, calibration, repeatability, and the key optical metrics that matter for production readiness. Attendees will leave with a clear, practical framework for testing modern AI-era hardware that combines electronics + photonics.
Trainer
