The Reshaping of Moore's Law with Advanced Packaging

Day 0 | Monday, 4 May 2026 | 08:30 - 17:30 

Room @my7-8, Level 1A, MITEC

As transistor scaling slows under the physical limits of lithography, the semiconductor industry is entering a new era—one where innovation is driven not just by node shrink, but by how chips are integrated and packaged.

This workshop explores how advanced packaging is redefining the trajectory of Moore’s Law. Participants will gain insight into cutting-edge approaches such as heterogeneous integration and chiplet architectures, enabling continued performance growth beyond traditional scaling limits.

We will delve into key packaging technologies, including wafer-level packaging, fan-out wafer and panel-level solutions, 3D integration, and embedded packaging—highlighting how each enhances transistor density and system performance, along with the associated technical challenges. The session will also cover next-generation interconnect and bonding techniques, including thermocompression and hybrid bonding used in advanced die stacking solutions such as SoIC-X and SoIC-P.

In addition, the workshop will examine evolving interposer architectures (2.1D, 2.3D, 2.5D and beyond), including platforms such as CoWoS-S, CoWoS-L, and CoWoS-R. It will also explore emerging interposer materials like glass substrates—covering their benefits, fabrication processes, technical challenges, and supply chain landscape in supporting the continued evolution of Moore’s Law.