Dr. Rama SHUKLA

Rama Shukla A Semiconductor Industry Veteran with Over 40 Years of Experience

Rama is a seasoned expert in the field of integrated circuit (I.C.) technology and product development, with a track record of leading and delivering innovative solutions for silicon front end and backend technologies, silicon components and systems level packaging, and technology and products planning, design, development, and high-volume manufacturing deployments. He has held senior leadership technical and operational positions at some of the world's leading semiconductor companies, such as Intel Corporation, Qualcomm Datacenter Technologies, and Western Digital Corporation, as well as two technology start-ups. He is currently the Vice President of Flash Products packaging at Western Digital Corporation, USA.

Rama has been a key driver of numerous industry initiatives throughout his career, including developing and driving the transformation of Intel CPU interconnects design and process to Flip Chip on Organic Substrates, leading to a whole new generation of semiconductor packaging industry ecosystem, that is state of the art today. For this achievement, he received the IEEE Manufacturing Technology of the Year Award in 2000. He is a passionate technologist with many technical publications and patents in the field of semiconductor silicon processing and I.C. packaging.

Rama holds a Ph.D. in Materials Science and Engineering from the University of California, Berkeley and a master’s degree from the Indian Institute of Technology, Kanpur, India.

Presentation Title

Flash Memory Packaging - At the Crossroads?

Abstract

In this new era of explosive data growth and trillion-dollar semiconductor market projections in the near future, semiconductor technology scaling has reached crossroads, creating opportunities for disruptions. The onslaught of Artificial Intelligence (AI) driven compute architectures and associated hardware has further accelerated the emergence of advanced 3D packaging technologies involving hybrid integration, Wafer-to-Wafer, Chip-on-Wafer, and Chip-to-Chip 3D hybrid integration.

Flash Memory-based products continue to evolve in this era of explosive data growth, driving the need for ever higher capacities, scaling up performance and power efficient architectures, miniaturized and near chip scale form factors, -to serve a diverse set of markets. In this regard, Hybrid Integration technology building blocks will be examined for relevance to Flash Memory products packaging requirements, that naturally tend to require high die count 3D Chip-to-Chip stacks.

While traditional package technologies for chip and system level packaging for Flash Memories (Stacked die BGA’s, SSD’s, Cards) will continue to evolve and thrive, the density/performance and emerging compute architectures present new opportunities for further innovations, that should drive the industry ecosystem to develop and deliver at scale, advanced 3D stacking and chip scale packaging technologies.

This talk will attempt to outline the available state of the art Flash Memory/packaging technologies practiced today and highlight key technology building blocks/innovations needed, system-technology co-optimization in this new era considering various tradeoffs between performance, cost and form factor; and need for the industry ecosystem to collaborate and evolve to support cost-effective high-volume infrastructure towards this purpose.

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