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AI for Product Testing Forum

Day 2 | Wednesday, 6 May 2026 | 09:30 - 17:30 

Novel 1, Level 1A, MITEC

Artificial intelligence is transforming IC testing by enabling smarter, faster, and more cost-effective solutions. From AI-driven fault detection and diagnosis to predictive analytics for yield improvement, these advancements address the growing complexity of modern integrated circuits. By automating test processes and enhancing accuracy, AI-powered testing accelerates time-to-market while reducing costs. This forum explores the latest innovations and applications of AI in reshaping the future of IC testing.

More Information will be available soon. Stay Tuned!

Agenda

09:30
Welcome and Introduction
09:40
Accelerating Test Engineering with Agentic AI in Era of Complexity
Mr. TAN Kheng How | Principal Technical Consultant, Advantest Corporation | SEMI Southeast Asia Advanced Product Testing Technical Committee
10:05
Presentation TBA
Mr. Stuart PEARCE | Senior Director, ATE & Test Instrument, AEM
10:30
Industrial Trend: AI Empowered Silicon Lifecycle Management (SLM)
Mr. Wu YANG | Director, Technical Programs - Tessent Silicon Lifecycle Solutions, Siemens EDA
10:55
Break and Networking
11:15
The AI Surge: Overcoming High-Volume Challenges in SiPh Wafer-Level Testing
Mr. LOO Joon Seng | Senior Technical Marketing Engineer, Nexustest 
Dr. Jeffrey LAM | Chief Technology Officer, CompoundTek | Chairman, SEMI Southeast Asia Advanced Product Testing Technical Committee
11:40
Smarter Yield Ramp: Leveraging Advanced Testing and Dynamic Fault Isolation
Mr. CHEN Changqing | Deputy Director, GlobalFoundries
12:05
Cutting-Edge X-Ray CT & Generative AI Utilization Will Bring High-Pass-Yield Mass Production
Mr. Kiyoshi MURAKAMI | Senior General Manager, Omron Corporation
12:30
Appreciation, Lunch and Networking
13:35
Welcome and Introduction
13:40
The Future of Product & Test is Agentic
Mr. Venkatesh DURAISAMY | Director, Data Engineering, Sandisk
14:05
Accelerating Artificial Intelligence in Product Testing to Enable “Self-Healing” Test Pattern Generation
Mr. Muthuramu GURUSAMY | Associate Vice President, Pre-Post Silicon, Tessolve Semiconductor
14:30
AI in DFT: From RTL Intent to Silicon Learning
Mr. R. Selvakumar RAJAGOPAL | Senior Principal Engineer, DFX Architect, Intel Corporation
14:55
Controlling Temperature of High Power AI Devices
Mr. Ernest BLANCO | Systems Engineer, Cohu
15:20
Break and Networking
15:40
From Specs to Validated Silicon: How AI Is Rewriting Product Testing for the Trillion-Dollar Semiconductor Era
Mr. Ali KAMALY | Co-Founder & Chief Executive Officer, TestFlow
16:05
Autonomous Fabs: How Agentic AI is Transforming Yield, Quality, and Efficiency
Panel Discussion
Moderator: Mr. Muthuramu GURUSAMY | Associate Vice President, Pre-Post Silicon, Tessolve Semiconductor
Panelists:
Mr. TAN Kheng How | Principal Technical Consultant, Advantest Corporation | SEMI Southeast Asia Advanced Product Testing Technical Committee
Ms. Sugantha RAJAKUMARI M. | Global AI and Supply Chain Leader, Genpact
Mr. Venkatesh DURAISAMY | Director, Data Engineering, Sandisk
17:15 -
17:30
Appreciation and Closing Remarks
Program is subject to changes.

Featured Speakers

Mr Tan Kheng How_1000x1000

Mr. TAN Kheng How

Principal Technical Consultant,
Advantest Corporation | SEMI Southeast Asia Advanced Product Testing Technical Committee
Mr Wu Yang_1000x1000

Mr. Wu YANG

Director, Technical Programs - Tessent Silicon Lifecycle Solutions,
Siemens EDA